A well-de ned schedule for stimuli and responses in Software Use 3 of 9 barcode in Software A well-de ned schedule for stimuli and responses

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3.3.3 A well-de ned schedule for stimuli and responses use software code-39 generating tocreate barcode code39 on software Visual Studio .NET 2003 Another importa Code 39 Extended for None nt choice refers to the timewise sequence of key events that repeat within every stimulus/response cycle, and to their relative timing. Poor timing may cause a gate-level model to report hundreds of hold-time violations per clock cycle during a simulation run, for instance, whereas a purely algorithmic model is simply not concerned with physical time. To complicate things further, engineers are often required to co-simulate an extracted gate-level netlist for one circuit block with a delayless model for some other part of the same design.

. 16 17. M o delSim by M entor Graphics is one such pro duct, for instance. In section 4.9.4. 3.3 REUSING THE SAME FUNCTIONAL GAUGE THROUGHOUT THE ENTIRE DESIGN CYCLE expect resp golden model stimuli generator report appli acqui model under test actual resp stimuli appli model under test acqui report b) a). actual resp golden model report stimuli appli model under test acqui stimuli appli acqui model under test actual resp report interm resp acqui model under test appli actual resp stimuli source code assembler program stimuli machine code appli golden model report acqui appli model under test actual resp stimuli stimuli test pattern generator expect resp stimuli generator golden model appli acqui expect resp Fig. 3.10 Softw Software barcode 3/9 are modules from which testbenches can be assembled to serve a variety of needs.

A setup that operates with a functional gauge previously stored on disk (a), a setup that generates stimuli and expected responses at run time (b), and an arrangement suitable for designs that implement involutory mappings (c). Alternatives for using a golden model as a reference (d,e); (e) addresses the special case where the stimuli exist as a piece of source code for a program-controlled processor. Options for preparing stimulus/response pairs (f,g).

. Observation 3.1 2. To be useful for comparing circuit models across multiple levels of abstraction, a testbench must schedule all major events in such a way as to respect the limitations imposed by all formalisms and tools involved in circuit speci cation, design, simulation, and test combined.

Formalisms and tools are meant to include automata theory, HDLs, RTL models, gate-level netlists (whether delayless or backannotated with timing data), simulation software, and automated test equipment (ATE). In their choice of a schedule, many circuit designers and test engineers tend to be misled by the speci c idiosyncrasies of one such instrument. Key events Consider some synchronous digital design.

18 The most important events that repeat in every clock cycle during both simulation and test then include. We assum e the barcode 3 of 9 for None p opular single-phase edge-triggered clo cking discipline where there is no di erence b etween clo ck cycle and com putation p erio d, see section 6.2.2 for details.

. Architectures of VLSI Circuits The The The The The application of a new stimulus denoted as (for Application), acquisition and evaluation of the response denoted as (for Test), recording of a stimulus/response pair for further use denoted as (for storage), active clock edge symbolically denoted as , and passive clock edge denoted as (mandatory but of subordinate signi cance).. When these even bar code 39 for None ts are ordered in an ill-advised way, the resulting schedules most often turn out to be incompatible. Exchanging functional gauges between software simulation and hardware testing then becomes very painful, if not impossible. The existence of a problem is most evident when supposedly identical simulation runs must be repeated many times over, ddling around with the order and timing of these events just to make the schedule t with the automated test equipment (ATE) at hand.

A suspicion always remains that such belated manipulations of test vectors cannot be trusted because any change to the sequence of events or to their timing raises the question of whether the original and the modi ed simulation runs are equivalent, that is, whether they are indeed capable of uncovering exactly the same set of functional aws. A coherent stimulus/response schedule The schedule of g.3.

11 has been found to be portable across the entire VLSI design and test cycle. Its formal derivation is postponed to section 3.7.

Observation 3.13. At the RTL and lower levels, any consistent testbench shall provide a clock signal even if the MUT is of purely combinational nature, log one stimulus/response pair per clock cycle, and have all clock edges, all stimulus applications, and all response acquisitions occur in a strictly periodic fashion, symbolically denoted as ( = ) .

. via state trans ition function via output function cause o(k 1) s(k) i(k) o(k) i(k+1) observable effect s(k+1) o(k+1) i(k+2) simulation time clock signal observable effect.
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