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10.3 GROUND BOUNCE AND SUPPLY DROOP use none none creator todevelop none for none Jasper Reports over/undershoots is none none the loss of stored data. Excessive ground bounce thus causes a digital circuit s behavior to become unpredictable and so renders it useless as part of a system. Milder forms have the circuit function correctly under optimum conditions but make it susceptible to external circumstances.

It is, therefore, absolutely essential to keep ground bounce within the bounds circumscribed by the noise margins of the technology.. 10.3.2 Where do large switching currents originate In static CMOS circ none none uits, the most important switching currents are typically drawn by output pad drivers due to the important o -chip load capacitances they must handle and the extremely wide transistors they include to do so. This explains why ground bounce is also known as simultaneous switching output noise (SSO noise or SSN). di(t)/dt noise is yet another synonym, and we will shortly see why.

Huge switching currents are by no means limited to pad drivers, since a thousand or so internal nodes that switch at the same time can cause spikes of similar magnitude. A major contribution to switching currents arises from clocking. Keep in mind that a clock event causes many circuit nodes other than the clock net nodes to toggle too.

In the case of the CPU 21064 by Digital Equipment Corp., for instance, it was found that ground bounce was equivalent to a cumulated capacitance of 12.5 nF while the capacitance of the clock net alone was 3.

2 nF. Another important source of transient currents that is often overlooked stems from transitory bu er contentions where the o -going three-state driver has not yet released a net before the on-going driver starts to pull in the opposite direction. Although very short-lived in logically correct designs, transient currents matter when strong bu ers are involved.

. 10.3.3 How severe is the impact of ground bounce A rough first-order approximation The subsequent tabl e taken from [301] quanti es the parasitic elements for a few packages of di erent construction including contributions from bond wires.. package type (64 68 none none pins) series resistance [ ] parallel capacitance [pF] series inductance [nH]. ceramic DIP 1.1 7 22 worst pin of plastic pin grid DIP array 0.1 0.2 4 2 36 7 chip carrier 0.2 2 7 Numerical data of o none for none n-chip wiring parasitics are given next for two digital CMOS processes. A generous power/ground line of xed width and signal lines of minimum widths are compared across all metal layers. Where two numbers are given, the rst one refers to the bottom and the second one to the top metal layer.

Line lengths and line spacings are the same throughout.. Design of VLSI Circuits line length 10 mm, none for none spacing 1 m line width [nm] series resistance [ ] capacitance to substrate [pF] series inductance3 [nH]. process A 250 nm 5M 1P Al supply signal 50 000 320 to 420 11 to 7.2 1700 to 860 15 to 2.4 0.

46 to 0.14 3.8 8.

2 to 8.0. process B 130 nm 8M none for none 1P Cu supply signal 50 000 160 to 400 14 to 5.4 4400 to 680 28 to 2.7 0.

52 to 0.12 3.8 8.

8 to 8.0. Now consider an output pad driver as shown in g.10.5.

The series impedance Zg in the current path to system ground is formed by on-chip interconnect lines, bond wire, and package lead. It includes a resistive part Rg and an inductive part Lg . The ground bounce voltage, i.

e. the di erence between on-chip and system ground potentials, is obtained as ug (t) = Rg ig (t) + Lg dig (t) dt (10.5).

where ig (t) is none none the superposition of the driver s output current and the crossover current that ows through the complementary MOSFETs while they are in the process of switching.. system power pin chip Zp on-chip power power supply + --. Zo final driver pair on-chip ground ig(t) Cl Zg ug(t) pin ul (t). system ground Fig. 10.5 Equivalent circuit for a CMOS output that drives a capactive load. According to [302], the line inductance was estim ated as L 200 10 l log w h +4 w h (10.4). where l denotes the length and w the width of the line. h indicates the distance that vertically separates the m etal line from the back m etal surface carrying the chip. Q uantities are expressed in [m ] and [H] resp ectively; the num eric gures given ab ove were obtained for h = 500 m .

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