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15.1 EVOLUTION PATHS FOR CMOS TECHNOLOGY use software code 39 full ascii generation tointegrate barcode 3 of 9 on software Web app field acts on channel from 1 side gate dielectric current flow SiGe yoke S from 2 sides G D SiN insulator from 4 sides from 2 or 3 sides current flow D n+ n+ pS gate dielectric G Si fin D gate dielectric Fig. 15.3 Topological options for future devices.

State-of-the-art ultra-thin-body SOI MOSFET (a), planar double-gate MOSFET (b), n-FET (c), and gate-all-around transistor (d) (simpli ed).. Fig. 15.4 Two multi-gate n-F Software barcode 3 of 9 ETs connected in series (source In neon, reprinted with permission).

. 15.1.3 Vertical integration Taking advantage of the third Software 3 of 9 barcode dimension holds the promise of increasing density much beyond what device scaling alone would permit. Yet, be cautioned that heat evacuation severely limits the amount of power that can possibly be dissipated in a truly three-dimensional volume..

Technology of VLSI Circuits Stacking one layer of MOSFETs Code 3 of 9 for None on top of a layer underneath is essentially achieved by making the wafer surface perfectly at by way of chemical mechanical polishing (CMP) before depositing and patterning another set of silicon, poly, and interlevel dielectric layers to form the next upper layer of devices. Making sure that the thin lms of silicon deposited are monocrystalline and of good quality is a critical element of the process [421]. 3D integration is more likely to be adopted for memories than for random logic because their tiled layouts does not ask for too much routing resources and because layout density remains an extremely strong competitive advantage.

4 Also, only parts sold in very high quantities can compensate for the larger mask count associated with vertical integration. At the time of writing (2007), antifuse-based PROMs are expected to hit the market soon. Prototypes of SRAMs where MOSFETs are stacked three levels high and interconnected using contact plugs and short metal straps have also been fabricated [422].

The 6-transistor bit cell is reported to occupy a mere 25F 2 . Others suggest using germanium-on-insulator (GOI) FETs with metal gates as a second layer of devices [409]. Alternative techniques that tap the third dimension essentially by stacking ordinary microchips are discussed in section 11.

4.7 in the context of packaging..

15.1.4 The search for better semiconductor materials High-mobility semiconductors A MOSFET s gain factor and, h ence, a CMOS circuit s operating speed directly depend on carrier mobility . Although strained silicon o ers a substantial bene t over plain silicon, the search for semiconductor materials with still higher carrier mobilities continues.5 Germanium, from which early BJTs had been manufactured in the 1950s, features electron and hole mobilities more than twice as high as in silicon.

What had led to the demise of Ge in favor of Si as base material for transistors and ICs were the lack of a stable oxide and signi cant leakage currents as a consequence of a narrower bandgap. Now that the traditional SiO2 oxides are bound to be replaced anyway, Ge may, or might not, reappear along with high-permittivity gate dielectrics and metal gates, all the more so, as its lower processing temperatures tend to make it compatible with a wider range of materials. The usage of germanium-on-insulator (GOI) wafers is currently being investigated for the 45 nm and later generations with the idea of getting a grip on subthreshold leakage by slashing junction areas much as in ultra-thin-body SOI technology, see g.

14.32. A limiting factor is the comparatively low electrical eld that Ge is able to sustain.

Even higher electron mobilities are observed in compound semiconductors such as gallium arsenide (GaAs, III V) and indium phosphide (InP, III V). Devices such as hetero FETs (HFET) and heterobipolar junction transistors (HBT) fabricated from these materials have been demonstrated to exhibit much higher transit frequencies than their silicon counterparts do. However, the fact that Si logic reaches a point where wiring rather than gate delay dominates a circuit s operating.

Three-dim ensional structures Code-39 for None have in fact b een well established in DRAM s ever since buried trench capacitors m ade their app earance in the 1 M ibit generation. M anufacturing the access transistor vertically along the wall of the capacitor or on top of it app ears a natural extension to further squeeze the bit cell. Key physical characteristics of sem iconductor m aterials are listed in app endix D.

3 while strained silicon and SiGe are discussed in section 14.3.4.

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